Delay Minimization for Zero-Skew Routing
نویسنده
چکیده
Delay minimization methods are proposed for zero-skew routings. A delay-time estimation formula is derived, which can be used as an objective function to be minimized in zero-skew routing algorithms. Moreover, the optimum wire width is formulated. Experimental results show that our methods with a clustering-based algorithm achieve 50% reduction of the delay time on benchmark data with 3000 pins. Department of Computer Science, Princeton University and C&C Systems Research Laboratories, NEC Corporation
منابع مشابه
Zero-Skew Clock Routing Trees With Minimum Wirelength
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we present the Deferred-Merge Embedding (DME) algorithm, which in linear t...
متن کاملProcess-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling
Process-variation induced skew has become one of the major contributors to the clock-skew in advanced technologies. Since process-variation induced skew is roughly proportional to clock-delay, it is preferable to design zero-skew clock-trees and have minimum clock-delay to reduce both unintentional and process-variation induced skews. In this paper, we propose a zero-skew buffered clock-tree sy...
متن کاملA Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing
In order to achieve multi-GHz operation frequency for VLSI design, clock networks need to be designed in a very elaborated manner and be able to deliver prescribed useful skews rather than merely zero-skew. Although traditional zero-skew clock routing methods can be extended directly to prescribed skews, they tend to result in excessive wirelength as the differences among delay-targets for cloc...
متن کاملMinimum Wirelength Zero Skew Clock Routing Trees with Buffer Insertion
Zero skew clock routing is an issue of increasing importance in the realm of VLSI design. As a result of the increasing speeds of on-chip clocks, zero skew clock tree construction has become critical for the correct operation of high performance VLSI circuits. In addition, in an effort to both reduce power consumption and the deformation of clock signals at synchronizing elements on a chip, a m...
متن کامل5 Conclusions and Directions for Future Work 4 Experimental Results
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we rst present the Deferred-Merge Embedding (DME) algorithm, which embeds ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1993